In order to construct computer systems capable of processing large amounts of data, it is useful to employ multiple individual processors in a single system. One exemplary multiple processor system is the PowerPC symmetric multiple processor ("SMP") system which operates in accordance with the common hardware reference platform ("CHRP") architecture. This system is described in detail in "PowerPC Microprocessor Common Reference Platform: A System Architecture," ISBN 1-55860-394-8, available from IBM. However, combining several individual processors which are simultaneously capable of running in a single system, presents certain difficulties for the system designer. For example, when a multiprocessor system is first powered on, it is conventional that one processor is selected as the "master" to execute the system open firmware for starting, or "booting" a client operating system. Other processors must be put into a halt, or stopped state which does not interfere with the operation of the master processor. If one of the other processors were to come out of the stopped state while the master was booting the system, it is possible that it would begin accessing system memory, e.g., to perform a memory test, or testing I/O adapters, etc. This could cause coherency problems in system memory resulting in a failure of the boot operation.
Also, the CHRP architecture requires that the run time abstraction software ("RTAS") must ensure that a processor in a stopped state will not check stop, or otherwise fail if a machine check or system reset exception, also referred to as a system reset interrupt ("SRI"), occurs. Thus, although all processors in the stopped state will receive the exception, they must perform a null action and remain in the stopped state.
Some of these problems can be alleviated if all the processors used in the system are provided with a hardware implemented stop state. However, many processors, for example, the PowerPC family of processors, do not have a hardware implemented stop state. Moreover, a hardware implemented stop state may not always provide the flexibility required by system designers.
Accordingly, it is an object of the present invention to provide a method for implementing a stopped state for a processor in a multiprocessor system which overcomes these problems. Additional objects and advantages will become apparent in view of the following disclosure.